Current consumer electronic devices use memory devices. For example, mobile electronic devices such as digital cameras, portable digital assistants, portable audio/video players and mobile terminals continue to require mass storage memories, preferably non-volatile memory with ever increasing capacities and speed capabilities. Non-volatile memory and hard disk drives are preferred since data is retained in the absence of power, thus extending battery life.
While existing memory devices operate at speeds sufficient for many current consumer electronic devices, such memory devices may not be adequate for use in future electronic devices and other devices where high data rates are desired. For example, a mobile multimedia device that records high definition moving pictures is likely to require a memory module with a greater programming throughput than one with current memory technology. While such a solution appears to be straightforward, there is a problem with signal quality at such high frequencies, which sets a practical limitation on the operating frequency of the memory. The memory communicates with other components using a set of parallel input/output (I/O) pins, the number of which depends on the desired configuration. The I/O pins receive command instructions and input data and provide output data. This is commonly known as a parallel interface. High speed operation may cause communication degrading effects such as cross-talk, signal skew and signal attenuation, for example, which degrades signal quality.
In order to incorporate higher density and faster operation on the system boards, there are two design techniques: serial interconnection configurations and parallel interconnection configurations such as multi-dropping. These design techniques may be used to overcome the density issue that determines the cost and operating efficiency of memory swapping between a hard disk and a memory system. However, multi-drop has a shortcoming relative to the serial interconnection of memory systems. For example, if the number of multi-drop memory system increases, as a result of loading effect of each pin, delay time also increases so that the total performance of the multi-drop system is degraded by the multi-drop connection caused by the wire resistor-capacitor loading and the pin capacitance of the memory device. A serial link in a device such as a memory device may utilize a single pin input that receives all address, command, and data serially. The serial link may provide a serial interconnection configuration to control command bits, address bits, and data bits effectively through the serial interconnection configuration. By providing a serial interconnection configuration, a memory device identifier (ID) number is assigned to each device on a chained configuration. Memory devices may be dynamic random access memories (DRAMs), static random access memories (SRAMs) or Flash memories.
For slower operating system applications, logic circuit combinations to capture data streams can be acceptable. However, in the case of high speed operation, the correct data capturing from single serial port to the assigned registers can not be ensured because of fast clock operation during command interpretation.